回頭來時路，Verilog 再體驗

原由

在整理個人硬碟的時候, 發現不少個人青壯時期寫的一些 Verilog 設計檔案(Behavior Language), 一時心癢, 想回味一下。於是, 就把Xilinx Vivado安裝了起來。不裝不知道, 裝了嚇一跳, 本來只是想吃一碗 “回味的泡麵” 過過癮, 想說簡單的 “小鍋子” 就該夠用了, 沒想到它卻幫我蓋了個 “中央廚房”！表列至少要 50GB 的安裝硬碟空間, 實際裝好已經逼近100GB了, 歷時三、四小時 , 也許是退休比較閒, 我就這麽傻傻地等它裝完了！

( AMD 買 Xilinx, Intel 買Altera, 嗯, 是不是也該裝一下Altera來比一比！？看看誰能 “扶龍” ?)

既然頭都洗了, 那, 就洗徹底一點吧！

安裝 Xilinx Vivado

$Xilinx Unified 2022.1 Installer - Select Destination Directory Select Destination Directory Choose installation options such as location and shortcuts. - Installation Option Select the installation directo C: \Xilinx Installation location(s Download locatio XILINX - Select shortcut and file association opti Create program group entries Xilinx Design Tools Create desktop shortcuts Create file associations Apply shortcut & file association selections O Current user o All users Disk Space Required Download Size: Disk Space Required: Final Disk Usage: Disk Space Available: 50.6 GB 143.96 84.12 663.51 GB copyright @ 1986-2022 Xilinx, Inc. All rights reserved. < Back Next > Cancel$

Xilinx Unified 2022.1 Installer - Installation Progress Installation Progress Downloading files (86.02 MB | 50.60 6B) 4 h and 8 m(s) left at 4 MB/sec. Install... Final Processing... copyright @ 1986-2022 Xilinx, Inc. All rights reserved. XILINX UltraFAS1 Design Methodology Comprehensive design methodology enables accelerated and predictable design cycles < Back Install Cancel

實際大小

X Ⅲ - 內容一共用大小 : 大小 : 女全性以的 93.6 GB 000 , 558 , 5 , 176 喞 1 GB 00L136 , 547 0 喞 30L265 , 39 28 炙 2022 年 6 月 15 日 , 上牛 1017 : 32

實在有點好奇, 用 treesize工具檢查一下

試用

先不追根究底, 直接試用看看

建立計畫

Vivado File Flow Tools Window Help VIVADO' ML Editions Quick Start Create Project > Open Project > Open Example Project > Q- Ouick Access

提供設計源碼資料夾的位置

New project VIVADO ML Editions XlLlNk Create a New Vivado Project This wizard will guide you through the creation of a new project. TO create a Vivad0 project you Will need to provide a name and a location for your project files. Next, you Will specify the type Of you'll be working With. Finally, you Will specify your project sources and choose a default part. c: Sack Fin ish Cancel

New project Project Name Enter a name for your project and specify a directory where the project data files will be stored project name: tsi_ff0 project location: Create project subdirectory Project will be created at: < Back Next Fin ish Cancel

添加源碼, 有漏掉的話, 之後還可以再添加

只是要看看設計的 “邏輯功能和行為” , 先不給限制

New project Add Constraints (optional) Specify or create constraint files for physical and timing constraints. +41 —It Cl Copy constraints files into project use Add Files or Create File buttons below < Back Next Fin ish Cancel

只是要看看設計的 “邏輯功能和行為”, 就不挑晶片了

加入要模擬的源碼, 一般就是把模擬樣本 (test vector / pattern) 和設計的源碼寫在一起 (串在一起)

Add Sources VIVADO ML EditMs XlLlNk Add Sources This guides you through the process Of adding and creating sources for your project O Add or greate constraints O Add or create design sources • Add or create simulation sources < Back Next Cancel

試跑, 有錯的話, 會有警告或錯誤訊息

依照訊息的提示, 一一解決出現錯誤的位置

發現有漏掉設計源碼檔案

繼續加入設計源碼

tsi fifo - [C:/rnyXiIinxNeriIog/tsi-fifo/Isi Eile Edit Flow Tools Reports Add Sources... Close p Checkpoint Constraints Simulation Waveform T ext Editor Export Print. Ctrl

Add Sources VIVADO ML EditMs XlLlNk Add Sources This guides you through the process Of adding and creating sources for your project O Add or greate constraints • Add or create design sources O Add or create simulation sources < Back Next Cancel

檢視已加入的設計源碼

PROJECT MANAGER - tsi MO Sources Design Sources ) • tsi_Mo (tsi_fifo.v) (1) dll_standard ts_pkts_rom Constraints Simulation Sources ( sim_l (I) ) tsi_Mo_test (tsi_Mo_test.v) (3) utility Sources Hierarchy Libraries Compile Order

再試跑一次

tsi fifo - Eile Edit Flow Flow Navigator Tools PROJECT MANAGER Settings Add Sources Language Templates Catalog IP INTEGRATOR Create Block Design Open Block Design Generate Block Design v SIMULATION Run Simulation RTL ANALYSIS > Open Elaborated Design SYNTHESIS Run Synthesis

只跑 “邏輯行為” 模擬 ( Behavioral Simulation)

SIMULATION Run %nulation RTL ANALYS > Open El SYNTHESIS Run Synthe a Run Behavioral Simulation aun aun Run Run Post•Synthesis Functional Simulation Post•Synthesis Timing Simulation Post-Implementation Functional Simulation post-Implementation Timing Simulation

依然發生錯誤, 2004年的Xilin產出的 IP, 現在的Vivado不認得(或者不存在)

之前使用Xilinx的倍頻 IP在 Vivado使用似乎有問題!?

Generating a 4X Clock

Sparty’s Favorite Recipes 019

Ingredients:

- Any Spartan-II Device
- 2.1i Development System
- VHDL or Verilog

Nutritional Analysis:

- DLLs: 2
- BUFGs: 2
- CLBs: 1

Instructions

By connecting two DLL circuits each implementing a 2x clock multiplier in series as shown below, a 4x clock multiply can be implemented with zero skew between registers in the same device. When using this circuit it is vital to use the SRL16 cell to reset the second DLL after the initial chip reset, so that the second DLL will recognize the change of frequencies when the input changes from a 1x (25/75) waveform to a 2x (50/50) waveform.

VHDL

— DLL 2X and 4X Example
—
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity dll_standard is
port (CLKIN : in std_logic;
RESET : in std_logic;
CLK2X : out std_logic;
CLK4X : out std_logic;
LOCKED: out std_logic);
end DLL_standard;

architecture structural of DLL_standard is

signal CLKIN_w, RESET_w, CLK2X_DLL, CLK2X_g, CLK4X_DLL,
CLK4X_g : std_logic;
signal LOCKED2X, LOCKED2X_delay, RESET4X,
LOCKED4X_DLL : std_logic;
signal logic1 : std_logic;

begin

logic1 <= ‘1’;

clkpad : IBUFG port map (I=>CLKIN, O=>CLKIN_w);
rstpad : IBUF port map (I=>RESET, O=>RESET_w);

dll2x : CLKDLL port map (CLKIN=>CLKIN_w, CLKFB=>CLK2X_g, RST=>RESET_w,
CLK0=>open, CLK90=>open, CLK180=>open,
CLK270=>open, CLK2X=>CLK2X_DLL, CLKDV=>open,
LOCKED=>LOCKED2X);

clk2xg : BUFG port map (I=>CLK2X_DLL, O=>CLK2X_g);

rstsrl : SRL16 port map (D=>LOCKED2X, CLK=>CLK2X_g, Q=>LOCKED2X_delay,
A3=>logic1, A2=>logic1, A1=>logic1, A0=>logic1);

RESET4X <= not LOCKED2X_delay;

dll4x : CLKDLL port map (CLKIN=>CLK2X_g, CLKFB=>CLK4X_g, RST=>RESET4X,
CLK0=>open, CLK90=>open, CLK180=>open,
CLK270=>open, CLK2X=>CLK4X_DLL, CLKDV=>open,
LOCKED=>LOCKED4X_DLL);

clk4xg : BUFG port map (I=>CLK4X_DLL, O=>CLK4X);
lckpad : OBUF port map (I=>LOCKED4X_DLL, O=>LOCKED);

CLK2X <= CLK2X_g;
CLK4X <= CLK4X_g;

end structural;

Verilog

// DLL 2X and 4X Example
//

module DLL_standard (CLKIN, RESET, CLK2X, CLK4X, LOCKED);
input CLKIN, RESET;
output CLK2X, CLK4X, LOCKED;

wire CLKIN_w, RESET_w, CLK2X_DLL, CLK4X_DLL, LOCKED2X;
wire LOCKED2X_delay, RESET4X;
wire logic1;

assign logic1 = 1’b1;

IBUFG clkpad (.I(CLKIN), .O(CLKIN_w));
IBUF rstpad (.I(RESET), .O(RESET_w));

CLKDLL dll2x (.CLKIN(CLKIN_w), .CLKFB(CLK2X), .RST(RESET_w),
.CLK0(), .CLK90(), .CLK180(), .CLK270(),
.CLK2X(CLK2X_DLL), .CLKDV(), .LOCKED(LOCKED2X));

BUFG clk2xg (.I(CLK2X_DLL), .O(CLK2X));
SRL16 rstsrl (.D(LOCKED2X), .CLK(CLK2X), .Q(LOCKED2X_delay),
.A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1));

assign RESET4X = !LOCKED2X_delay;

CLKDLL dll4x (.CLKIN(CLK2X), .CLKFB(CLK4X), .RST(RESET4X),
.CLK0(), .CLK90(), .CLK180(), .CLK270(),
.CLK2X(CLK4X_DLL), .CLKDV(), .LOCKED(LOCKED_DLL));

BUFG clk4xg (.I(CLK4X_DLL), .O(CLK4X));
OBUF lckpad (.I(LOCKED_DLL), .O(LOCKED));

endmodule

Related Information

XAPP174

來自 <http://ebook.pldworld.com/_semiconductors/Xilinx/DataSource%20CD-ROM/Rev.1%20(Q2-2000)/docs/rp00007/rp007ad.htm>

2004年的IP可能已過時, 在Vivado找不到或者不存在, 最後決定在 Vivado 的 “IP 庫” 裡重新創建一個倍頻模組 (PLL type)

(頭都洗了, 不差再洗身體和腳, 就洗個徹底吧!)

在 IP Catalog 裡尋找 clock 相關的 IP設計

訂製一個屬於自己規格的 IP 模塊

客製自己的規格需求

Enable 0 一 02 : 名 uts Outputs fo 「 •J 一 00k d power_down ResetType ActiveHigh ActiveLOW Ⅱ 凵

確認需求無誤之後產出 IP, 會產出在計畫所在位置的資料夾裡

Generate Output products The following output products will be generated Preview (OOC per IP) fil Instantiation Template Synthesized Checkpoint (.dcp) Structural Simulation Synthesis Options o Global • Out of context per Run Settings • On local host: o Generate scripts only o DA not launch Apply Number of jobs: 4 Skip

Generate Output Products o Out-of-context module run was launched for generating output products.

修改 simulation test file, 改用新產出的 IP模塊

殘留的舊 IP 模塊先留著, 應該不影響後續跑模擬

修改模擬設定, 加大模擬的時間 (預設只有 1000ns)

SIMULATION Run Simulati > RTL ANALYSIS SYNTHESIS Run Synthesi > Open Synth TCI Console Messages Simulation Settings. Reset Behavioral Simulation Reset Post-synthesis Functional Simulation Reset post-synthesis Timing Simulation Reset Post-Implementation Functional Simulation Reset Post-implementation Timing Simulation

開始正式跑模擬

SIMULATION Run Simul > RTLANALYS SYNTHESIS Run Sy Open S TCI Console Run Behavioral Simulation Messages Run Post•Synthesis Functional Simulation Run Post•Synthesis Timing Simulation Run post-Implementation Functional Simulation Run post-Implementation Timing Simulation : 00

模擬結果輸出

Untitled Name reset clk_27m psync_in 1' pvld_in psync_out pvld_out Value 00

到此, 一碗 “回味的泡麵” 算是煮好了!

回頭來時路，Verilog 再體驗

阿福雲端記事

回頭來時路，Verilog 再體驗

原由

安裝 Xilinx Vivado

試用

發佈留言取消回覆

原由

安裝 Xilinx Vivado

試用

發佈留言 取消回覆

發佈留言取消回覆